1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
2. Related Art
As digitalization and broadbandization have rapidly progressed in precision electronic devices such as portable telephone devices, portable information terminals, and digital appliances, there is an increasing demand for semiconductor devices with multiple functions, high-performance semiconductor devices, less expensive semiconductor devices, and high-density semiconductor devices. In this trend, there is a need for a novel mounting technique for mounting different kinds of devices such as logic devices, memories, sensors, and passive elements on a substrate at high density at low costs. Examples of those devices include Si devices such as CMOSLSI, high-speed devices containing GaAs, light emitting devices, and MEMS (Micro-Electro-Mechanical Systems).
MEMS is a generic term for minute structures manufactured by a silicon fine processing technique. The MEMS technique is expected to be applied in various fields, such as pressure sensors, acceleration sensors, ink jet printers, and filters. To construct a system with devices using the MEMS technique, it is necessary to integrate a MEMS device and a semiconductor chip (a logic, an analog amplifier, a memory, or the like) on the same substrate.
To solve the problems in the conventional mounting techniques such as SMT (Surface Mounting Technique) and MCM (Multi Chip Module) so as to meet the above need, the following two integration techniques have been developed. One of the two techniques is called System-On-Chip (SOC), by which more than one device is formed directly on one chip. By this technique, high device integration is achieved, and minute global wires can be used between the devices, since the devices are formed on one chip. Accordingly, higher integration and higher performance can be achieved with a thinner package. However, there are restrictions on the devices that can be integrated. For example, it is difficult to form a device containing a crystalline material such as GaAs on a Si substrate, because of the difference in lattice constant and the difference in linear expansion coefficient. Also, a device such as a LSI requiring high-precision design rules and a device formed by low-precision design rules cannot be efficiently produced in the same procedures. Particularly, all the processes need to be changed, when a new device is incorporated. Therefore, the costs for development of a new device are high, and the development period is long.
The other technique is called System-In-Package (SIP). By this technique, chips are formed separately from one another, and each of them is mounted on a substrate that is a so-called interposer. Since the devices can be formed independently of one another, there are few restrictions on the devices. Also, when a new system is developed, the existing chips can be used. Accordingly, the development cost is low, and the development period is short. However, the problem with this technique is that the interposer and the chips are connected with bonding wires and bumps or the likes. Therefore, it is difficult to achieve high density in chip arrangement, and to form minute wires and a thinner package.
In this trend, a pseudo SOC technique is now being developed as a new integration technique for achieving the advantages of both SOC and SIP. By the pseudo SOC technique, different kinds of devices are rearranged and recombined with an adhesive resin, and a semiconductor device formed on one substrate is virtually produced. Since the existing chips can be incorporated as in the case of SIP, a new device can be developed in a short period of time at low costs. Also, an insulating layer or a metal thin film is formed over a substrate having different kinds of chips integrated thereon, and a global multilayer wiring layer is formed between the chips. With this arrangement, the same minute wiring structure as that of SOC can be formed, and higher performance and higher integration can be achieved.
JP-A 2004-103955 (KOKAI) discloses a semiconductor device having semiconductor chips buried in a resin as described above. According to JP-A 2004-103955 (KOKAI), a corrective element is used for correcting deformation caused in resin layers at the time of cure of the resin material, and a resin layer having chips buried therein is formed on a stacked structure formed with a resin layer and the corrective element. The corrective element is made of a material such as glass, carbon, or aramid resin, which has a smaller thermal expansion coefficient and a greater Young's modulus than the burying resin. With such a corrective element, shrinkage of resin during the cure shrinkage process is restricted, and the warpage is corrected. By the technique disclosed in JP-A 2004-103955 (KOKAI), however, the semiconductor device is a stacked structure of the resin and the corrective element. Therefore, the device cannot be made thinner, and high integration cannot be achieved.
As described above, by the conventional integration technique for burying chips in resin, a corrective element needs to be added so as to reduce the warpage caused at the time of cure. Therefore, the device cannot be made thinner, and higher integration cannot be achieved.